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I2C(R) CMOS 8 x 12 Unbuffered Analog Switch Array With Dual/Single Supplies ADG2128
FEATURES
I2C-compatible interface 3.4 MHz high speed I2C option 32-lead LFCSP_VQ (5 mm x 5 mm) Double-buffered input logic Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual 5 V/single +12 V operation On resistance 35 maximum Low quiescent current < 20 A
GENERAL DESCRIPTION
The ADG2128 is an analog cross point switch with an array size of 8 x 12. The switch array is arranged so that there are eight columns by 12 rows, for a total of 96 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 96 switches can be addressed and configured through the I2Ccompatible interface. Standard, full speed, and high speed (3.4 MHz) I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2128 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power-on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm x 5 mm LFCSP_VQ.
APPLICATIONS
AV switching in TV Automotive infotainment AV receivers CCTV Ultrasound applications KVM switching Telecom applications Test equipment/instrumentation PBX systems
FUNCTIONAL BLOCK DIAGRAM
VDD VSS VL
ADG2128
SCL SDA
INPUT REGISTER AND 7 TO 96 DECODER
1 LATCHES 96 LDSW
1 8 x 12 SWITCH ARRAY 96 LDSW X0 TO X11 (I/O)
A2 A1 A0
GND
Y0 TO Y7 (I/O)
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05464-001
ADG2128 TABLE OF CONTENTS
Features ..............................................................................1 Applications.......................................................................1 General Description .........................................................1 Functional Block Diagram ..............................................1 Revision History ...............................................................2 Specifications.....................................................................3 I2C Timing Specifications............................................7 Timing Diagram ...........................................................8 Absolute Maximum Ratings............................................9 ESD Caution..................................................................9 Pin Configuration and Function Descriptions...........10 Typical Performance Characteristics ...........................11 Test Circuits.....................................................................15 Terminology ....................................................................17 Theory of Operation ......................................................18 RESET/Power-On Reset ............................................18 Load Switch (LDSW)................................................. 18 Readback ..................................................................... 18 Serial Interface................................................................ 19 High Speed I2C Interface........................................... 19 Serial Bus Address...................................................... 19 Writing to the ADG2128............................................... 20 Input Shift Register .................................................... 20 Write Operation ......................................................... 22 Read Operation .......................................................... 22 Evaluation Board............................................................ 24 Using the ADG2128 Evaluation Board ................... 24 Power Supply .............................................................. 24 Schematics................................................................... 25 Outline Dimensions....................................................... 27 Ordering Guide .......................................................... 27
REVISION HISTORY
5/06--Rev. 0 to Rev. A Added I2C Information......................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 5 Changes to Table 4............................................................................ 9 Changes to Figure 24...................................................................... 14 Changes to Terminology Section.................................................. 17 Changes to Figure 35...................................................................... 23 Changes to the Ordering Guide.................................................... 27 1/06--Revision 0: Initial Version
Rev. A | Page 2 of 28
ADG2128 SPECIFICATIONS
VDD = 12 V 10%, VSS = 0 V, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 1.
B Version -40C to +25C +85C VDD - 2 V 30 35 32 37 45 50 4.5 8 2.3 3.5 14.5 18 0.03 0.03 11 18.5 170 185 210 250 0.04 40 42 57 9 4 20 30 35 32 37 45 50 4.5 8 2.3 3.5 14.5 18 0.03 0.03 11 18.5 170 185 210 250 0.04 90 210 16.5 -69 -63 -76 0.4 0.6 -3.5 2.0 0.8 0.005 1 Input Capacitance, CIN 7 7 0.005 1 210 16.5 -69 -63 -76 0.4 0.6 -3.5 2.0 0.8 Y Version -40C to +25C +125C VDD - 2 V 42 47 62 10 5 22
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON
Unit V max typ max typ max typ max typ max typ max typ max A typ A typ pF typ pF typ ns typ ns max ns typ ns max % typ dB typ MHz typ MHz typ dB typ dB typ dB typ % typ typ pC typ V min V max A typ A max pF typ
Conditions
VDD = +10.8 V, VIN = 0 V, IS = -10 mA VDD = +10.8 V, VIN = +1.4 V, IS = -10 mA VDD = +10.8 V, VIN = +5.4 V, IS = -10 mA VDD = +10.8 V, VIN = 0 V, IS = -10 mA VDD = 10.8 V, VIN = 0 V to +1.4 V, IS = -10 mA VDD = 10.8 V, VIN = 0 V to +5.4 V, IS = -10 mA VDD = 13.2 V VX = 7 V/1 V, VY = 1 V/7 V VX = VY = 1 V or 7 V
On Resistance Matching Between Channels, RON On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION DYNAMIC CHARACTERISTICS 2 COFF CON tON tOFF THD + N PSRR -3 dB Bandwidth Off Isolation Channel-to-Channel Crosstalk Adjacent Channels Nonadjacent Channels Differential Gain Differential Phase Charge Injection LOGIC INPUTS (Ax, RESET)2 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN
RL = 300 , CL = 35 pF RL = 300 , CL = 35 pF RL = 10 k, f = 20 Hz to 20 kHz, VS = 1 V p-p f = 20 kHz; without decoupling; see Figure 24 Individual inputs to outputs 8 inputs to 1 output RL = 75 , CL = 5 pF, f = 5 MHz RL = 75 , CL = 5 pF, f = 5 MHz
190 255
195 260
RL = 75 , CL = 5 pF, f = 5 MHz RL = 75 , CL = 5 pF, f = 5 MHz VS = 4 V, RS = 0 , CL = 1 nF
Rev. A | Page 3 of 28
ADG2128
Parameter LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD ISS IL Interface Inactive Interface Active: 400 kHz fSCL Interface Active: 3.4 MHz fSCL 0.3 2 0.1 0.2 0.4 1.2
1 2
B Version -40C to +85C +25C 0.7 VL VL + 0.3 -0.3 0.3 VL 0.005 1 0.05 VL 7 0.4 0.6 1 0.05 1 0.05 1
Y Version -40C to +125C +25C 0.7 VL VL + 0.3 -0.3 0.3 VL 0.005 1 0.05 VL 7 0.4 0.6 1 0.05 1 0.05 1 0.3 2 0.1 0.2 0.4 1.7
Unit V min V max V min V max A typ A max V min pF typ V max V max A max A typ A max A typ A max A typ A max mA typ mA max mA typ mA max
Conditions
VIN = 0 V to VL
ISINK = 3 mA ISINK = 6 mA
Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs = 0 V or VL
-HS model only
Temperature range is as follows: B version: -40C to +85C; Y version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 28
ADG2128
VDD = +5 V 10%, VSS = -5 V 10%, VL = 5 V, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. 1 Table 2.
B Version -40C to +25C +125C Y Version -40C to +25C +125C VDD - 2 V 34 40 50 55 66 75 4.5 8 17 20 34 42 0.03 0.03 6 9.5 170 200 210 250 0.04 300 18 -66 -62 -79 1.5 1.8 -3 2.0 0.8 0.005 1 Input Capacitance, CIN LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH Input Low Voltage, VINL 7 0.7 VL VL + 0.3 -0.3 0.3 VL 7 0.7 VL VL + 0.3 -0.3 0.3 VL 0.005 1 45 65 85 9 23 45 34 40 50 55 66 75 4.5 8 17 20 34 42 0.03 0.03 6 9.5 170 200 210 250 0.04 90 300 18 -64 -62 -79 1.5 1.8 -3 2.0 0.8 50 70 95 10 25 48
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON
Unit V max typ max typ max typ max typ max typ max typ max A typ A typ pF typ pF typ ns typ ns max ns typ ns max % typ dB typ MHz typ MHz typ dB typ dB typ dB typ % typ typ pC typ V min V max A typ A max pF typ V min V max V min V max
Conditions
VDD = +4.5 V, VSS = -4.5 V, VIN = VSS, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VIN = 0 V, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VIN = +1.4 V, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VIN = VSS, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VIN = VSS to 0 V, IS = -10 mA VDD = +4.5 V, VSS = -4.5 V, VIN = VSS to +1.4 V, IS = -10 mA VDD = 5.5 V, VSS = 5.5 V VX = +4.5 V/-2 V, VY = -2 V/+4.5 V VX = VY = -2 V or +4.5 V
On Resistance Matching Between Channels, RON On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS Channel Off Leakage, IOFF Channel On Leakage, ION DYNAMIC CHARACTERISTICS 2 COFF CON tON tOFF THD + N PSRR -3 dB Bandwidth Off Isolation Channel-to-Channel Crosstalk Adjacent Channels Nonadjacent Channels Differential Gain Differential Phase Charge Injection LOGIC INPUTS (Ax, RESET)2 Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current, IIN
RL = 300 , CL = 35 pF RL = 300 , CL = 35 pF RL = 10 k, f = 20 Hz to 20 kHz, VS = 1 V p-p f = 20 kHz; without decoupling; see Figure 24 Individual inputs to outputs 8 inputs to 1 output RL = 75 , CL = 5 pF, f = 5 MHz RL = 75 , CL = 5 pF, f = 5 MHz
215 255
220 260
RL = 75 , CL = 5 pF, f = 5 MHz RL = 75 , CL = 5 pF, f = 5 MHz VS = 0 V, RS = 0 , CL = 1 nF
Rev. A | Page 5 of 28
ADG2128
Parameter Input Leakage Current, IIN Input Hysteresis Input Capacitance, CIN LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL Floating State Leakage Current POWER REQUIREMENTS IDD ISS IL Interface Inactive Interface Active: 400 kHz fSCL Interface Active: 3.4 MHz fSCL 0.3 2 0.1 0.1 0.4 0.3
1 2
B Version -40C to +25C +125C 0.005 1 0.05 VL 7 0.4 0.6 1 0.05 1 0.05 1
Y Version -40C to +25C +125C 0.005 1 0.05 VL 7 0.4 0.6 1 0.005 1 0.005 1 0.3 2 0.1 0.1 0.4 0.3
Unit A typ A max V min pF typ V max V max A max A typ A max A typ A max A typ A max mA typ mA max mA typ mA max
Conditions VIN = 0 V to VL
ISINK = 3 mA ISINK = 6 mA
Digital inputs = 0 V or VL Digital inputs = 0 V or VL Digital inputs = 0 V or VL
-HS model only
Temperature range is as follows: B version: -40C to +85C; Y version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. A | Page 6 of 28
ADG2128
I2C TIMING SPECIFICATIONS
VDD = 5 V to 12 V; VSS = -5 V to 0 V; VL = 5 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted (see Figure 2). Table 3.
Parameter 1 fSCL Conditions Standard mode Fast mode High speed mode 2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 Standard mode Fast mode High speed mode2 Standard mode Fast mode Standard mode Fast mode High speed mode2 Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum ADG2108 Limit at TMIN, TMAX Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 0 0 0 4.7 0.6 160 4 0.6 160 4.7 1.3 4 0.6 160 20 + 0.1 CB
B
Unit kHz kHz MHz MHz s s ns ns s s ns ns ns ns ns s s ns ns s s ns s s ns s s s s ns ns ns ns ns ns ns ns ns
Description Serial clock frequency
t1
tHIGH, SCL high time
t2
tLOW, SCL low time
t3
tSU;DAT, data setup time
t4 3
3.45 0.9 70 150
tHD;DAT, data hold time
t5
tSU;STA, setup time for a repeated start condition
t6
tHD;STA, hold time for a repeated start condition
t7 t8
tBUF, bus free time between a stop and a start condition tSU;STO, setup time for a stop condition
t9
1000 300 80 160 300 300 80 160
tRDA, rise time of SDA signal
10 20 20 + 0.1 CBB 10 20
t10
tFDA, fall time of SDA signal
Rev. A | Page 7 of 28
ADG2128
Parameter 1 t11 Conditions Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Standard mode Fast mode High speed mode2 CB = 100 pF maximum CB = 400 pF maximum Fast mode High speed mode2 ADG2108 Limit at TMIN, TMAX Min Max 1000 20 + 0.1 CBB 300 10 20 20 + 0.1 CB
B
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description tRCL, rise time of SCL signal
t11A
40 80 1000 300 80 160 300 300 40 80 50 10
tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
10 20 20 + 0.1 CBB 10 20 0 0
t12
tFCL, fall time of SCL signal
tSP
Pulse width of suppressed spike
1
Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line; tR and tF are measured between 0.3 VDD and 0.7 VDD. High speed I2C is available only in -HS models. 3 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
2
TIMING DIAGRAM
t2
SCL
t11
t12
t6
t6
t4
t3 t1
t5 t10
t8 t9
SDA
t7
P
S
S
P
05464-002
S = START CONDITION P = STOP CONDITION
Figure 2. Timing Diagram for 2-Wire Serial Interface
Rev. A | Page 8 of 28
ADG2128 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs Digital Inputs Continuous Current 10 V on Input; Single Input Connected to Single Output 1 V on Input; Single Input Connected to Single Output 10 V on Input; Eight Inputs Connected to Eight Outputs Operating Temperature Range Industrial (B Version) Automotive (Y Version) Storage Temperature Range Junction Temperature 32-Lead LFCSP_VQ JA Thermal Impedance Reflow Soldering (Pb Free) Peak Temperature Time at Peak Temperature Rating 15 V -0.3 V to +15 V +0.3 V to -7 V -0.3 V to +7 V VSS - 0.3 V to VDD + 0.3 V -0.3 V to VL + 0.3 V or 30 mA, whichever occurs first 65 mA 90 mA 25 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-40C to +85C -40C to +125C -65C to +150C 150C 108.2C/W 260C (+0/-5) 10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 28
ADG2128 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND RESET SDA
26
A2
A0
SCL
A1
32
31
30
29
28
27
VSS 1 NC X0 X1 X2 X3 X4 X5
2 3 4 5 6 7 8 9
VL
25 24
PIN 1 INDICATOR
VDD NC X11 X10 X9 X8 X7 X6
05464-003
23 22
ADG2128
12 x 8 TOP VIEW (Not to Scale)
21 20 19 18 17
10
11
12
13
14
15
16
Y2
Y4
Y3
Y6
Y0
Y1
NC = NO CONNECT
Exposed Paddle Soldered to VSS Figure 3. Pin Configuration
Table 5. Pin Function Descriptions 1
Pin No. 1 2, 23 3 to 8, 17 to 22 9 to 16 24 25 26 27 28 29 30 31 32
1
Mnemonic VSS NC X0 to X11 Y0 to Y7 VDD VL SDA SCL A0 A1 A2 RESET GND
Description Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin should be tied to GND. No Connect. Can be inputs or outputs. Can be inputs or outputs. Positive Power Supply Input. Logic Power Supply Input. Digital I/O. Bidirectional open drain data line. External pull-up resistor required. Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data into the device. External pull-up resistor required. Logic Input. Address pin that sets the least significant bit of the 7-bit slave address. Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address. Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address. Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0. Ground Reference Point for All Circuitry on the ADG2128.
It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.
Rev. A | Page 10 of 28
Y5
Y7
ADG2128 TYPICAL PERFORMANCE CHARACTERISTICS
200 TA = 25C 180 IDS = 10mA 160 140
RON ()
90 TA = 25C IDS = 10mA 80 VDD = 7.2V VSS = 0V VDD = +8V
RON ()
70 VDD = 8V 60
120 100 80 60 40 20
VSS = -5V VDD = +5V
50 VSS = 0V VDD = +12V
05464-007
VDD = 8.8V 40
05464-025
0 -5 -4 -3 -2 -1 0
30
1
2
3
4
5
6
7
8
9 10 11 12
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 4. Signal Range
85 TA = 25C IDS = 10mA VDD/VSS = 4.5V 65
RON ()
Figure 7. RON vs. Source Voltage, VDD = 8 V 10%
80 70 60 50 RON () 40 TA = +25C 30 20
05464-017
75
VDD = +5V VSS = -5V IDS = 10mA TA = +85C
TA = +125C
VDD/VSS = 5V 55
45 VDD/VSS = 5.5V
TA = -40C
35
25 -5.5
-4.5
-3.5
-2.5
-1.5
-0.5
0.5
1.5
0 -5
-4
-3
-2
-1
0
1
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 5. RON vs. Source Voltage, Dual 5 V Supplies
70 65 60 55
RON () RON ()
Figure 8. RON vs. Temperature, Dual 5 V Supplies
60 VDD = 12V VSS = 0V IDS = 10mA TA = +85C
TA = 25C IDS = 10mA
VDD = 10.8V
TA = +125C
50
50 45 40 35 30 25 20 0 1 2 3 4
VDD = 12V
40 TA = +25C TA = -40C 20
30
VDD = 13.2V 10
05464-018 05464-027
5
6
7
8
0
0
1
2
3
4
5
6
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 6. RON vs. Supplies, VDD = 12 V 10%
Figure 9. RON vs. Temperature, VDD = 12 V
Rev. A | Page 11 of 28
05464-026
10
ADG2128
80 70 60 50
RON ()
18 VDD = 8V VSS = 0V IDS = 10mA TA = +85C 16 TA = +125C
LEAKAGE CURRENTS (nA)
VDD = 12V VSS = 0V
Y CHANNELS, VBIAS = 7V X CHANNELS, VBIAS = 7V
14 12 10 8 6 4 2
05464-013
40 TA = +25C 30 TA = -40C 20 10 0
Y CHANNELS, VBIAS = 1V
0 -2 0 20 40 60 80 100 120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE VOLTAGE (V)
TEMPERATURE (C)
Figure 10. RON vs. Temperature, VDD = 8 V
16 14
LEAKAGE CURRENTS (nA)
Figure 13. On Leakage vs. Temperature, 12 V Single Supply
9 8 7
LEAKAGE CURRENTS (nA)
VDD = +5V VSS = -5V
VDD = 12V VSS = 0V X, Y CHANNELS; VBIAS = 7V ON X CHANNEL; 1V ON Y CHANNEL
12 10 8 6 4 2 0
6 5 4 3 2 1
X CHANNELS, VBIAS = +4V
Y CHANNELS, VBIAS = -2V
X, Y CHANNELS; VBIAS = 1V ON X CHANNEL; 7V ON Y CHANNEL
05464-012
05464-014
0 -1 0 20 40 60 80 100 120
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. On Leakage vs. Temperature, Dual 5 V Supplies
12 10
LEAKAGE CURRENTS (nA)
Figure 14. Off Leakage vs. Temperature, 12 V Single Supply
0 -0.5 -1.0
VDD = 5V VSS = -5V
8 6 4 2 0 -2 X, Y CHANNELS; VBIAS = +4V ON X CHANNEL; -2V ON Y CHANNEL
CHARGE INJECTION (pC)
-1.5 -2.0 -2.5 -3.0 -3.5 -4.0 VDD = +5V, VSS = -5V VDD = +12V, VSS = 0V
05464-030
X, Y CHANNELS; VBIAS = -2V ON X CHANNEL; +4V ON Y CHANNEL
05464-015
-4.5 -5.0 -5 -3 -1 1 3 5 7 9 11
0
20
40
60
80
100
120
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
Figure 12. Off Leakage vs. Temperature, Dual 5 V Supplies
Figure 15. Charge Injection vs. Supply Voltage
Rev. A | Page 12 of 28
05464-011
ADG2128
0 240 -1 220 200 -2 -3 -4 -5 -6
05464-029 05464-022
180 TON 160 140 120 100 -40
VDD = 5V, VSS = 0V
VDD = 12V, VSS = 0V
INSERTION LOSS (dB)
TOFF
TON/TOFF (ns)
-7 -8 10
VDD = +5V VSS = -5V TA = 25C 1k 100k FREQUENCY (Hz) 10M 1G
-20
0
20
40
60
80
100
120
10G
TEMPERATURE (C)
Figure 16. TON/TOFF Times vs. Temperature
-2
Figure 19. One Input to Eight Outputs Bandwidth, 5 V Dual Supply
-10 -20 VDD = +5V TO +12V VSS = -5V TO 0V TA = 25C
-3
-30
INSERTION LOSS (dB)
INSERTION LOSS (dB)
05464-020
-4
-40 -50 -60 -70 -80 -90 -100 -110 10 1k 100k FREQUENCY (Hz) 10M 1G
05464-023
-5
-6
-7
-8 10
VDD = +5V VSS = -5V TA = 25C 1k 100k FREQUENCY (Hz) 10M 1G 10G
Figure 17. Individual Inputs to Individual Outputs Bandwidth, Dual 5 V Supply
-1
Figure 20. Off Isolation vs. Frequency
-20
-2 -3 -4 -5 -6 -7 -8 10 VDD = 12V VSS = 0V TA = 25C 1k 100k FREQUENCY (Hz) 10M 1G
VDD = +5V TO +12V VSS = -5V TO 0V TA = 25C
INSERTION LOSS (dB)
INSERTION LOSS (dB)
-40
ADJACENT CHANNELS
-60
-80 NON-ADJACENT CHANNELS -100
05464-021
10G
-120 10
1k
100k FREQUENCY (Hz)
10M
1G
Figure 18. Individual Inputs to Individual Outputs Bandwidth, 12 V Single Supply
Figure 21. Crosstalk vs. Frequency
Rev. A | Page 13 of 28
05464-024
ADG2128
0.35 0.30 0.25 -40
IL (mA)
VDD = +5V VSS = -5V VL = 5V
VDD = 5V/12V VSS = -5V/0V TA = 25C -20 0.2V p-p RIPPLE SWITCH ON, WITHOUT DECOUPLING
ACPSRR (dB)
0
0.20 0.15 0.10 0.05 0
SWITCH OFF, WITHOUT DECOUPLING
-60
-80 VL = 3V -100
05464-016
WITH DECOUPLING
0
0.5
1.0
1.5
2.0
2.5
3.0
-120 100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 22. Digital Current (IL) vs. Frequency
1.8 1.6 1.4 1.2 IL (mA) 1.0 0.8 0.6 0.4
05464-019
Figure 24. ACPSRR
VL = 5V
0.2 0
VL = 3V
0
1
2
3 VLOGIC (V)
4
5
6
Figure 23. Digital Current (IL) vs. VLOGIC for Varying Digital Supply Voltage
Rev. A | Page 14 of 28
05464-028
ADG2128 TEST CIRCUITS
The test circuits show measurements on one channel for clarity, but the circuit applies to any of the switches in the matrix.
IDS V1
IOFF A
05464-031
X
Y
X
Y
IOFF A
05464-032
VS
RON = V1/IDS
VX
VY
VY
Figure 25. On Resistance
Figure 26. Off Leakage
Figure 27. On Leakage
0.1F
VDD
VSS
0.1F 9TH DATA BIT VOUT RL 300 CL 35pF VOUT 90%
05464-034
VDD X VX
VSS Y
50%
tOFF AND tON
GND
Figure 28. Switching Times, tON, tOFF
0.1 F
VDD
VSS
0.1 F
VDD RX VX X
VSS Y CL 1nF VOUT
SW ON DATA BIT
SW OFF
GND
QINJ = CL x VOUT
Figure 29. Charge Injection
VDD 0.1F VSS 0.1F NETWORK ANALYZER 50 VX Y RL 50 VOUT V GND RL 50 VOUT 0.1F VDD VSS 0.1F NETWORK ANALYZER 50 VX
VDD X
VSS
VDD X
VSS
50 Y
V GND
05464-036
05464-035
VOUT
VOUT
OFF ISOLATION = 20 log
VOUT VS
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
Figure 30. Off Isolation
Figure 31. Bandwidth
Rev. A | Page 15 of 28
05464-037
05464-033
NC
X
Y
ION
A
ADG2128
VDD 0.1F NETWORK ANALYZER VOUT RL 50 50 VX DATA BIT VSS 0.1F
VDD Y1 X2
VSS X1 Y2 R 50 GND R 50
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 32. Channel-to-Channel Crosstalk
Rev. A | Page 16 of 28
05464-038
ADG2128 TERMINOLOGY
On Resistance (RON) The series on-channel resistance measured between the X input/output and the Y input/output. On Resistance Match (RON) The channel-to-channel matching of on resistance when channels are operated under identical conditions. On Resistance Flatness (RFLAT(ON)) The variation of on resistance over the specified range produced by the specified analog input voltage change with a constant load current. Channel Off Leakage (IOFF) The sum of leakage currents into or out of an off channel input. Channel On Leakage (ION) The current loss/gain through an on-channel resistance, creating a voltage offset across the device. Input Leakage Current (IIN) The current flowing into a digital input when a specified low level or high level voltage is applied to that input. Input Off Capacitance (COFF) The capacitance between an analog input and ground when the switch channel is off. Input/Output On Capacitance (CON) The capacitance between the inputs or outputs and ground when the switch channel is on. Digital Input Capacitance (CIN) The capacitance between a digital input and ground. Output On Switching Time (tON) The time required for the switch channel to close. The time is measured from 50% of the logic input change to the time the output reaches 10% of the final value. Output Off Switching Time (tOFF) The time required for the switch to open. This time is measured from 50% of the logic input change to the time the output reaches 90% of the switch off condition. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitudes plus noise of a signal to the fundamental. -3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. Off Isolation The measure of unwanted signal coupling through an off switch. Crosstalk The measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Differential Gain The measure of how much color saturation shift occurs when the luminance level changes. Both attenuation and amplification can occur; therefore, the largest amplitude change between any two levels is specified and is expressed as a percentage of the largest chrominance amplitude. Differential Phase The measure of how much hue shift occurs when the luminance level changes. It can be a negative or positive value and is expressed in degrees of subcarrier phase. Charge Injection The measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Input High Voltage (VINH) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum input voltage for Logic 0. Output Low Voltage (VOL) The minimum input voltage for Logic 1. Input Low Voltage (VINL) The maximum output voltage for Logic 0. IDD Positive supply current. ISS Negative supply current.
Rev. A | Page 17 of 28
ADG2128 THEORY OF OPERATION
The ADG2128 is an analog cross point switch with an array size of 8 x 12. The 12 rows are referred to as the X input/output lines, while the eight columns are referred to as the Y input/output lines. The device is fully flexible in that it connects any X line or number of X lines with any Y line when turned on. Similarly, it connects any X line with any number of Y lines when turned on. Control of the ADG2128 is carried out via an I2C interface. The device can be operated from single supplies of up to 13.2 V or from dual 5 V supplies. The ADG2128 has many attractive features, such as the ability to reset all the switches, the ability to update many switches at the same time, and the option of reading back the status of any switch. All of these features are described in more detail here in the Theory of Operation section.
LOAD SWITCH (LDSW)
LDSW is an active high command that allows a number of switches to be simultaneously updated. This is useful in applications where it is important to have synchronous transmission of signals. There are two LDSW modes: the transparent mode and the latched mode. Transparent Mode In this mode, the switch position changes after the new word is written in. LDSW is set to 1. Latched Mode In this mode, the switch positions are not updated at the same time that the input registers are written to. This is achieved by setting LDSW to 0 for each word (apart from the last word) written to the device. Then, setting LDSW to 1 for the last word allows all of the switches in that sequence to be simultaneously updated.
RESET/POWER-ON RESET
The ADG2128 offers the ability to reset all of the 96 switches to the off state. This is done through the RESET pin. When the RESET pin is low, all switches are open (off), and appropriate registers are cleared. Note that the ADG2128 also has a poweron reset block. This ensures that all switches are in the off condition on power-up of the device. In addition, all internal registers are filled with 0s and remain so until a valid write to the ADG2128 takes place.
READBACK
Readback of the switch array conditions is also offered when in standard mode and fast mode. Readback enables the user to check the status of the switches of the ADG2128. This is very useful when debugging a system.
Rev. A | Page 18 of 28
ADG2128 SERIAL INTERFACE
The ADG2128 is controlled via an I2C-compatible serial bus. The parts are connected to this bus as a slave device (no clock is generated by the switch). 2. The peripheral whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse, known as the acknowledge bit. At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is 1 (high), the master reads from the slave device. If the R/W bit is 0 (low), the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses: eight data bits followed by an acknowledge bit from the receiver of the data. Transitions on the SDA line must occur during the low period of the clock signal, SCL, and remain stable during the high period of SCL, because a low-to-high transition when the clock is high can be interpreted as a stop signal. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition.
HIGH SPEED I2C INTERFACE
In addition to standard and full speed I2C, the ADG2188 also supports the high speed (3.4 MHz) I2C interface. Only the -HS models provide this added performance. See the Ordering Guide for details.
SERIAL BUS ADDRESS
The ADG2128 has a 7-bit slave address. The four MSBs are hard coded to 1110, and the three LSBs are determined by the state of Pin A0, Pin A1, and Pin A2. By offering the facility to hardware configure Pin A0, Pin A1, and Pin A2, up to eight of these devices can be connected to a single serial bus. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as when a high-to-low transition on the SDA line occurs while SCL is high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device.
3.
4.
Refer to Figure 33 and Figure 34 for a graphical explanation of the serial data transfer protocol.
Rev. A | Page 19 of 28
ADG2128 WRITING TO THE ADG2128
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
DB23 (MSB) 1 1 1 0 A2 A1 DB16 (LSB) A0 R/W DB15 (MSB) DB8 (LSB) DB7 (MSB) X X X X X X DB0 (LSB)
05464-004
DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0 DATA BITS
X
LDSW
DEVICE ADDRESS
DATA BITS
Figure 33. Data-Words
Table 6. Input Shift Register Bit Function Descriptions
Bit DB23 to DB17 DB16 Mnemonic 1110xxx R/W Description The MSBs of the ADG2128 are set to 1110. The LSBs of the address byte are set by the state of the three address pins, Pin A0, Pin A1, and Pin A2. Controls whether the ADG2128 slave device is read from or written to. If R/W = 1, the ADG2128 is being read from. If R/W = 0, the ADG2128 is being written to. Controls whether the switch is to be open (off ) or closed (on). If Data = 0, the switch is open/off. If Data = 1, the switch is closed/on. Controls I/Os X0 to X11. See Table 7 for the decode truth table. Controls I/Os Y0 to Y7. See Table 7 for the decode truth table. Don't care. This bit is useful when a number of switches need to be simultaneously updated. If LDSW = 1, the switch position changes after the new word is read. If LDSW = 0, the input data is latched, but the switch position is not changed.
DB15
Data
DB14 to DB11 DB10 to DB8 DB7 to DB1 DB0
AX3 to AX0 AY2 to AY0 X LDSW
As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines. Table 7 shows the truth table for these bits. Note the full coding sequence is written out for Channel Y0, and Channel Y1 to Channel Y7 follow a similar pattern. Note also that the RESET pin must be high when writing to the device. Table 7. Address Decode Truth Table
DB15 DATA 1 0 1 0 1 0 1 0 1 0 1 0 X X 1 0 1 0 1 0 DB14 AX3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 DB13 AX2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 DB12 AX1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 DB11 AX0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 DB10 AY2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. A | Page 20 of 28
DB9 AY1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DB8 AY0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Switch Configuration X0 to Y0 (on) X0 to Y0 (off ) X1 to Y0 (on) X1 to Y0 (off ) X2 to Y0 (on) X2 to Y0 (off ) X3 to Y0 (on) X3 to Y0 (off ) X4 to Y0 (on) X4 to Y0 (off ) X5 to Y0 (on) X5 to Y0 (off ) Reserved Reserved X6 to Y0 (on) X6 to Y0 (off ) X7 to Y0 (on) X7 to Y0 (off ) X8 to Y0 (on) X8 to Y0 (off )
ADG2128
DB15 DATA 1 0 1 0 1 0 X X 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 1 0 .. 1 DB14 AX3 1 1 1 1 1 1 1 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB13 AX2 0 0 1 1 1 1 1 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB12 AX1 1 1 0 0 0 0 1 1 0 0 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 DB11 AX0 1 1 0 0 1 1 0 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 0 0 .. 1 DB10 AY2 0 0 0 0 0 0 0 0 0 0 .. 0 0 0 .. 0 0 0 .. 0 1 1 .. 1 1 1 .. 1 1 1 .. 1 1 1 .. 1 DB9 AY1 0 0 0 0 0 0 0 0 0 0 .. 0 1 1 .. 1 1 1 .. 1 0 0 .. 0 0 0 .. 0 1 1 .. 1 1 1 .. 1 DB8 AY0 0 0 0 0 0 0 0 0 1 1 .. 1 0 0 .. 0 1 1 .. 1 0 0 .. 0 1 1 .. 1 0 0 .. 0 1 1 .. 1 Switch Configuration X9 to Y0 (on) X9 to Y0 (off ) X10 to Y0 (on) X10 to Y0 (off ) X11 to Y0 (on) X11 to Y0 (off ) Reserved Reserved X0 to Y1 (on) X0 to Y1 (off ) X11 to Y1 (on) X0 to Y2 (on) X0 to Y2 (off ) X11 to Y2 (on) X0 to Y3 (on) X0 to Y3 (off ) X11 to Y3 (on) X0 to Y4 (on) X0 to Y4 (off ) X11 to Y4 (on) X0 to Y5 (on) X0 to Y5 (off ) X11 to Y5 (on) X0 to Y6 (on) X0 to Y6 (off ) X11 to Y6 (on) X0 to Y7 (on) X0 to Y7 (off ) X11 to Y7 (on)
Rev. A | Page 21 of 28
ADG2128
WRITE OPERATION
When writing to the ADG2128, the user must begin with an address byte and R/W bit, after which the switch acknowledges that it is prepared to receive data by pulling SDA low. This address byte is followed by the two 8-bit words. The write operations for the switch array are shown in Figure 34. Note that it is only the condition of the switch corresponding to the bits in the data bytes that changes state. All other switches retain their previous condition. b. Enter the readback address for the X line of interest, the addresses of which are shown in Table 8. Note that the ADG2128 is expecting a 2-byte write; therefore, be sure to enter another byte of don't cares. (see Figure 35). The ADG2128 then places the status of those eight switches in a register that can be read back.
c. 2.
The second step involves reading back from the register that holds the status of the eight switches associated with your X line of choice. a. As before, enter the I2C address of the ADG2128. This time, set the R/W bit to 1 to indicate that you would like to read back from the device. As with a write to the device, the ADG2128 outputs a 2-byte sequence during readback. Therefore, the first eight bits of data out that are read back are all 0s. The next eight bits of data that come back are the status of the eight Y lines attached to that particular X line. If the bit is a 1, then the switch is closed (on); similarly, if it is a 0, the switch is open (off).
READ OPERATION
Readback on the ADG2128 has been designed to work as a tool for debug and can be used to output the status of any of the 96 switches of the device. The readback function is a 2-step sequence that works as follows: 1. Select the relevant X line that you wish to read back from. Note that there are eight switches connecting that X line to the eight Y lines. The next step involves writing to the ADG2128 to tell the part that you would like to know the status of those eight switches. a. Enter the I2C address of the ADG2128, and set the R/W bit to 0 to indicate that you are writing to the device.
SCL
b.
The entire read sequence is shown in Figure 35.
SDA
START COND BY MASTER ADDRESS BYTE
A2
A1
A0
R/W
ACK BY SWITCH
DATA
AX3
AX2
AX1
AX0
AY2
AY1
AY0
ACK BY SWITCH
x
x
x
x
x
DATA BYTE
x
x
LDSW
05464-005
DATA BYTE
ACK BY SWITCH
STOP COND BY MASTER
Figure 34. Write Operation
Table 8. Readback Addresses for Each X Line
X Line X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 RB7 0 0 0 0 0 0 0 0 0 0 0 0 RB6 0 0 1 1 0 0 1 1 0 0 1 1 RB5 1 1 1 1 1 1 1 1 1 1 1 1 RB4 1 1 1 1 1 1 1 1 1 1 1 1 RB3 0 1 0 1 0 1 0 1 0 1 0 1 RB2 1 1 1 1 1 1 1 1 1 1 1 1 RB1 0 0 0 0 0 0 0 0 1 1 1 1 RB0 0 0 0 0 1 1 1 1 0 0 0 0
Rev. A | Page 22 of 28
ADG2128
SCL SDA START COND BY MASTER ADDRESS BYTE A2 A1 A0 R/W RB7 ACK BY SWITCH RB6 RB5 RB4 RB3 RB2 RB1 RB0 ACK BY SWITCH x x x x x
DATA BYTE
x
x
x NO ACK BY SWITCH
STOP COND BY MASTER
DATA BYTE
SCL
SDA
START COND BY MASTER ADDRESS BYTE
A2
A1
A0
R/W
ACK BY SWITCH DUMMY READBACK BYTE ACK BY MASTER
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
NO ACK BY MASTER
STOP COND BY MASTER
READBACK BYTE
Figure 35. Read Operation
Rev. A | Page 23 of 28
05464-006
ADG2128 EVALUATION BOARD
The ADG2128 evaluation board allows designers to evaluate the high performance ADG2128 8 x 12 switch array with minimum effort. The evaluation kit includes a populated, tested ADG2128 printed circuit board. The evaluation board interfaces to the USB port of a PC, or it can be used as a standalone evaluation board. Software is available with the evaluation board that allows the user to easily program the ADG2128 through the USB port. Schematics of the evaluation board are shown in Figure 36 and Figure 37. The software runs on any PC that has Microsoft(R) Windows(R) 2000 or Windows XP installed.
USING THE ADG2128 EVALUATION BOARD
The ADG2128 evaluation kit is a test system designed to simplify the evaluation of the ADG2128. Each input/output of the part comes with a socket specifically chosen for easy audio/video evaluation. An application note is also available with the evaluation board and gives full information on operating the evaluation board.
POWER SUPPLY
The ADG2128 evaluation board can be operated with both single and dual supplies. VDD and VSS are supplied externally by the user. The VL supply can be applied externally, or the USB port can be used to power the digital circuitry.
Rev. A | Page 24 of 28
ADG2128
SCHEMATICS
Figure 36. EVAL-ADG2128EB Schematic, USB Controller Section
Rev. A | Page 25 of 28
05464-039
ADG2128
Figure 37. EVAL-ADG2128EB Schematic, Chip Section
Rev. A | Page 26 of 28
05464-040
ADG2128 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30 12 MAX
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 38. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG2128BCPZ-REEL 1 ADG2128BCPZ-REEL71 ADG2128BCPZ-HS-RL71 ADG2128YCPZ-REEL1 ADG2128YCPZ-REEL71 ADG2128YCPZ-HS-RL71 EVAL-ADG2128EB
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C
I2C Speed 100 kHz, 400 kHz 100 kHz, 400 kHz 100 kHz, 400 kHz, 3.4 MHz 100 kHz, 400 kHz 100 kHz, 400 kHz 100 kHz, 400 kHz, 3.4 MHz
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-32-3 CP-32-3 CP-32-3 CP-32-3 CP-32-3 CP-32-3
Z = Pb-free part.
Rev. A | Page 27 of 28
ADG2128 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05464-0-5/06(0)
Rev. A | Page 28 of 28

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